The present invention relates to flash memory devices, and more particularly, to flash memory devices including a ready/busy control circuit and methods of testing the same.
Typically, a series of test procedures are used to determine whether the characteristics of memory devices such as flash memory devices satisfy required specifications. If a flash memory device includes a defective chip which fails to satisfy the required specifications, the entire test process of the flash memory device may be affected by the defective chip. For example, if the defective chip fails to meet the requirements for programming time, the defective chip may not be able to complete all programming operations within a required time, in contrast to a good chip (i.e., a chip that passed a verification process), so that the entire testing time of the flash memory device may be increased.
Therefore, a flash memory device may include a chip disable fuse circuit that can be used to minimize or reduce the influence of a defective chip on the entire testing time of the flash memory device. If a defective chip is identified during a test, a fuse in the chip disable fuse circuit is cut out (i.e. open-circuited), which causes the defective chip to become permanently disabled. In other words, the defective chip is made completely inoperable, so that it cannot influence the test of the flash memory device.
FIG. 1 is a block diagram schematically illustrating a conventional flash memory device. Referring to FIG. 1, a conventional flash memory device includes a chip disable fuse circuit 15 and a chip enable control circuit 17 that function to reduce or minimize the influence of a defective chip on the test of the flash memory device.
When the fuse in the chip disable fuse circuit 15 is cut out, a chip disable signal DIS is activated. Subsequently, a chip enable signal nCE is forced to a logic high level in response to a control signal CECON generated in the chip enable control circuit 17. The chip enable signal nCE is a signal that indicates whether or not the flash memory device is enabled, and is externally input to the flash memory device through a chip enable pin /CE.
When the chip enable signal nCE has a logic high level, a command receipt circuit 11 does not process any external commands. In other words, when the chip enable signal nCE is at a logic high level, commands input into the command receipt circuit 11 are blocked, so that the commands cannot be delivered to a flash memory internal circuit 13 through the command receipt circuit 11. As a result, the flash memory internal circuit 13 is made inoperable.
Therefore, if the fuse of the chip disable fuse circuit 15 in the defective chip is cut out during the test, that defective chip becomes completely inoperable, and does not influence other chips during the test of the flash memory device.
Furthermore, the flash memory device includes a short current generation circuit 19 in order to readily determine whether or not the there is a failure during the test. When the chip disable signal DIS is generated, the short current generation circuit 19 forms an electrical short path to generate an electrical short current.
However, in the conventional flash memory device as described above, no commands are input to the internal circuit 13 of the flash memory device after the fuse of the chip disable fuse circuit 15 is cut out. Therefore, if a good chip is incorrectly determined to be defective due to an erroneous test or set-up process, and the fuse of the chip disable fuse circuit corresponding to that chip is cut out (i.e., a good chip is erroneously disabled), it is no longer possible to correct the state of the disabled chip.